SemiExpo 2022 » Making Chip Packaging Simpler
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24 March 2019

Packaging is emerging as one of the most critical elements in semiconductor design, but it’s also proving difficult to master both technically and economically.

The original role of packaging was simply to protect the chips inside, and there are still packages that do just that. But at advanced nodes, and with the integration of heterogeneous components built using different manufacturing processes, packaging is taking on a much broader and more strategic role. Many of the new packages are application-specific, and they are an integral part of the system architecture. They can help channel heat, improve performance, help to reduce power, and even safeguard signal integrity.

Typically called advanced packaging—to distinguish it from the standard plastic or ceramic type of packaging—this approach has been developed to enhance the reliability of advanced-node chips. In many cases, it also serves as an alternative way to overcome thermal and electrostatic limitations. This is particularly true for multi-chip packages, where a third dimension allows processors to access memories located above them or next to them using very high-speed connections. That can be significantly faster than sending signals from one end of a large chip to the other over skinny wires at 7nm, where heat buildup caused by resistance is problematic. In addition, it allows chip architects to scatter memories throughout the package to avoid contention for resources, which creates routing nightmares for designs with centralized memories.

But packaging is becoming every bit as complicated as developing a complex SoC. While advanced packaging has been ramping up for the past several years in server chips and mobile phones, there is not enough commonality yet for this to be considered mainstream. There are several key reasons for this:

  • Most of the companies that have adopted advanced packaging were pushing the limits on performance, but they hit a roadblock with the diminishing power/performance benefits of Moore’s Law. For these companies, cost was less of an issue than performance and form factor.
  • Nearly all of the early implementations were custom designs, using non-standard approaches to packaging. This required close collaboration between the chipmakers, the foundries and/or the OSATs. While it has proven effective, particularly for applications such as mobile phones and networking chips, those packages were developed for a specific application using very specific components.
  • Most mainstream chipmakers—those not at the leading-edge nodes—still have plenty of power/performance headroom at established nodes, where the vast majority of chips are being developed. This is aided by the fact that foundries have been aggressively adding options at those nodes, which are still significantly less expensive than 10/7nm or even 16/14nm. But as more standardized packaging becomes available, that could change because those companies will be able to mix and match different components.

Consensus about what works where is beginning to emerge. Packaging has been in an almost constant state of change over the past several years as packaging houses and foundries experiment with different ways to put chips together. Even within the same type of packaging approach, such as fan-out, there are chip first and chip last approaches. It’s also possible to add pillars on fan-outs, which add memory stacks on top of logic in a quasi-3D-IC configuration.

And in 2.5D, silicon interposers and organic interposers use a bridge either in the redistribution layer, or in the case of Intel’s Embedded Multi-Die Interconnect Bridge, across various elements to provide a super-fast in-package interconnect between heterogeneous chips.

“The package is now a major part of the operation of the system,” said Joao Geada, chief technologist at ANSYS. “We have reached the end of economic Moore’s Law scaling. When you need to build a big system, instead of throwing everything into a single process, now it’s a question of what’s the most economic process for what I’m trying to achieve. And typically, in a modern system design, that has multiple answers. You can optimize by targeting things to the appropriate process, but that means you still want to preserve the same kind of approximate footprint. And all of that has to be integrated into a single package. This is where all sorts of new challenges come in because the assumptions that a lot of this was built on—that you could make predictions about the behavior of a design in isolation without taking environmental context into account—stop being true.”

In effect, the divide-and-conquer design approach shifts from blocks on the same chip to chips in a package. And while the package reduces some physical effects, such as variation across a large die, it brings its own set of challenges.

“As the variation becomes a larger component of the spec, you have that many more occurrences in the edge of the distribution, and they are additive,” said David Fried, CTO at Coventor, a Lam Research company. “With a 50-core CPU, for example, you’re going to add in all of the standard design complexity with I/Os and memory. But you want to do it faster and the specs and the variation aren’t going away. If those variations don’t shrink commensurately, system engineering becomes that much more difficult. So is it easier if I crack this into five pieces? The system engineering gets a little easier. But it requires heterogeneous integration because you can’t just design everything the way you used to.”

What works where
This has led to a search for the best packaging options, and the amount of research done in this area by systems companies, universities, equipment makers, foundries and packaging houses has been enormous.

“We are seeing the introduction of more advanced system in package(SiP), fan-out on substrate, and 2.5D chip on wafer packages,” said Warren Flack, vice president of worldwide lithography applications at Veeco. “This is on top of the traditional flip-chip market, which continues to show growth.”

The shift toward more advanced packages presents several challenges. For example, high-density fan-out requires tighter pitches with finer redistribution layers (RDLs), which provide the electrical connections in the package. The latest high-density fan-out packages are migrating toward the 1µm line/space barrier and beyond. At these critical dimensions (CDs), fan-outs will provide better performance and cost.

“Redistribution layers with smaller critical dimensions enable reducing the total number of redistribution process levels in a fan-out package,” Flack said. “This, in turn, reduces the total packaging cost and improves yield for our customers. Currently, 1µm RDL is in low volume, but we expect that it will increase significantly over the next few years.”

Going to finer RDL CDs in the package presents some challenges, namely for lithography, which is the art of patterning features on chips and packages.

“Going to smaller features requires exposing with a shorter wavelength (i-line or Hg) and having a larger lens numerical aperture,” Flack said. “The major lithography challenges going forward for these advanced fan-out packages are imaging submicron RDL with high aspect ratios, minimizing overlay errors that occur from die shifting, extremely warped substrate handling, and support for very large 2.5D chip on wafer package sizes. Yield and productivity will drive the cost of adopting advanced fan-out packages. Only very high ASP (average selling price) devices can afford this kind of advanced packaging approach.”

That is expected to continue in the near term, but there are efforts underway to provide the same benefits in fan-outs, and fan-outs with chiplets, as more expensive approaches such as 2.5D where a silicon interposer is currently used. ASE, for example, reports adoption of its fan-out chip on substrate, which can support HBM2 memory. In the past, only 2.5D packages utilized HBM, which are modules of stacked DRAM. ASE has demonstrated the technology for heterogeneous and homogeneous server applications, as well as for AI chips and chiplets.

“This is intended to be an alternative to interposer solutions for these markets,” said John Hunt, senior director of engineering at ASE. “It provides a lower-cost solution, and actually has better electrical and thermal performance than a silicon interposer structure.”

This approach uses a fan-out composite die on a traditional ball-grid array substrate, which is basically the same type of substrate used in standard BGA and 2.5D interposer-based packages. The BGA provides the second level of “fan out” of the package, which is in addition to the finer fan-out chip-on-substrate bump pitch to a standard circuit board assembly pitch.

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